The Department of Electronics and Communication Engineering, Srinivas Institute of Technology, in association with STEADY, EDP, and IIC, successfully organized a workshop titled "Prototype Validation and Value Proposition Fit using the VLSI Design Cycle" on 27th July 2026.

The resource persons for the workshop were Ms. Sharanya and Ms. Sneha Rai from Vermatrix Edutech, Mangalore. The primary objective of the workshop was to familiarize students with the fundamentals of Very Large Scale Integration (VLSI) design and to demonstrate how innovative ideas can be transformed into functional integrated circuits through a systematic VLSI design cycle. Ms. Sharanya commenced the session by explaining the basics of VLSI, semiconductor technology, and the latest trends in chip design, highlighting the growing demand for VLSI professionals in the semiconductor industry.

She further provided a live demonstration of designing and simulating basic digital circuits by writing Verilog Hardware Description Language (HDL) code using EDA Playground, an open-source cloud-based platform widely used for learning and validating digital designs. The hands-on session enabled students to understand the complete workflow from coding to simulation and verification, thereby strengthening their practical understanding of digital IC design.

The workshop significantly enhanced the participants' understanding of the VLSI design process, Verilog programming, and digital circuit simulation using industry-relevant open-source tools. Students gained practical exposure to prototype validation techniques and learned how to evaluate the technical feasibility and value proposition of innovative semiconductor-based solutions. The session motivated students to explore VLSI-based product development, participate in semiconductor-focused hackathons and innovation challenges, and pursue careers in chip design, embedded systems, and semiconductor research.